High performance microprocessors with heat sink capabilities will likely be required to dissipate hundreds of watts from sub-volt power supplies in near and long-term microelectronic technology generations. A need exists for low cost and high pin count microelectronic package technology that can satisfy power supply and heat removal requirements within such chips.
The mechanical performance of a microelectronic package is important for wafer-level testing, protection, and reliability. Wafer-level testing requires simultaneous reliable contact to all die across a non-planar wafer surface. In-plane (i.e., x-y axis) compliance is generally required to account for thermal expansion between the chip and printed wiring board (or other attachment substrate). Wafer-level testing and burn-in demands significant out-of-plane (i.e., z-axis) compliance in order to establish reliable electrical contact between wafer-level pads and test-card or printed wiring board probes due to the non-planarity of each surface.
Unlike conventional packaging, wafer-level packaging (WLP) is a continuation of integrated circuit manufacturing. In WLP, additional masking steps can be used after fabricating die pads to simultaneously package all die across a wafer. A unique class of WLP is called “compliant wafer-level packaging” (CWLP). In CWLP, additional masking steps can be used after fabricating die pads to batch fabricate compliant x-y-z axis I/O leads between the die pads and the board pads. The use of compliant leads allows for the elimination of underfill between chip and substrate, and hence improves manufacturability and cost. A mechanically x-y-z flexible lead is formed between the die pad and the bump interconnection that would be joined with the board. Accordingly, there is a need in the industry for x-y-z compliant leads that provide high density, high electrical performance, low cost, and ability of batch fabrication.
Thus, a heretofore unaddressed need exists in the microelectronics industry to address the aforementioned deficiencies and/or inadequacies.